Cycle-accurate macro-models for RT-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic power estimation using the probabilistic contribution measure (PCM)
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the conference on Design, automation and test in Europe
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessor Architectures: From VLIW to Tta
Microprocessor Architectures: From VLIW to Tta
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework
IEEE Transactions on Computers
Block-wise Extraction of Rent's Exponents for an Extensible Processor
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
XTREM: a power simulator for the Intel XScale® core
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Using Transport Triggered Architectures for Embedded Processor Design
Integrated Computer-Aided Engineering
Microprocessors & Microsystems
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In this paper, a methodology for estimating area, energy consumption and execution time of an application executed on a specified processor is proposed. In addition, a design exploration process to find suitable processor architectures for a specific application is proposed. Cost and performance estimation is an important part of the exploration process. The actual cost estimation is based on predefined characterizations of cost and performance of resources stored in a database. The results show that the method is quick and its accuracy is sufficient for design space exploration.