Topology optimization for application-specific networks-on-chip
Proceedings of the 2004 international workshop on System level interconnect prediction
IBM Journal of Research and Development - POWER5 and packaging
Hardware cost estimation for application-specific processor design
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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It is envisioned that future system-on-chip hardwareplatform designs will be based on reuse of a customizableprocessor core. Consequently, being able to quicklyevaluate the key performance metrics associated withspecific points in the design space becomes essential.Development of an early design phase performanceestimation method for logic blocks of an extensibleprocessor core is described. The processor blocks weresystematically synthesized with varying constraints forreference and the corresponding Rent's exponents wereextracted from the results. The impact of synthesis-originated design space discontinuities on the accuracy ofphysical performance estimation was evaluated byapplying linear regression on the resulting design points.