Making graphs reducible with controlled node splitting
ACM Transactions on Programming Languages and Systems (TOPLAS)
Design space exploration algorithm for heterogeneous multi-processor embedded system design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Instruction-level power estimation for embedded VLIW cores
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Design and test space exploration of transport-triggered architectures
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Exploiting data forwarding to reduce the power budget of VLIW embedded processors
Proceedings of the conference on Design, automation and test in Europe
The TACO protocol processor simulation environment
Proceedings of the ninth international symposium on Hardware/software codesign
Power exploration for embedded VLIW architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Architectural differences of efficient sequential and parallel computers
Journal of Systems Architecture: the EUROMICRO Journal
Computation in the Context of Transport Triggered Architectures
International Journal of Parallel Programming
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures
Journal of Electronic Testing: Theory and Applications
Automated Design of an ASIP for Image Processing Applications (Research Note)
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
CC '02 Proceedings of the 11th International Conference on Compiler Construction
A Framework for Teaching (Re)Configurable Architectures in Student Projects
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
IEEE Transactions on Computers
Feedback driven instruction-set extension
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Fast Evaluation of Protocol Processor Architectures for IPv6 Routing
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A scalable, clustered SMT processor for digital signal processing
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Self-replication for reliability: bio-inspired hardware and the embryonics project
Proceedings of the 3rd conference on Computing frontiers
Energy efficiency vs. programmability trade-off: architectures and design principles
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A dynamically constrained genetic algorithm for hardware-software partitioning
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Effects of program compression
Journal of Systems Architecture: the EUROMICRO Journal
Self-replicating hardware for reliability: The embryonics project
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Very wide register: an asymmetric register file organization for low power embedded processors
Proceedings of the conference on Design, automation and test in Europe
Dual Antenna Receivers for High Data Rate Terminals
Wireless Personal Communications: An International Journal
Dual Antenna Receivers for High Data Rate Terminals
Wireless Personal Communications: An International Journal
Integrated code generation by using fuzzy control system
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Application-specific instruction set processor implementation of list sphere detector
EURASIP Journal on Embedded Systems
Proceedings of the 2008 ACM symposium on Applied computing
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Microprocessors & Microsystems
A software defined approach for common baseband processing
Journal of Systems Architecture: the EUROMICRO Journal
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
A Hardware-Software Design Framework for Distributed Cellular Computing
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Resource conflict detection in simulation of function unit pipelines
Journal of Systems Architecture: the EUROMICRO Journal
Dictionary-based program compression on customizable processor architectures
Microprocessors & Microsystems
Parallel Memory Architecture for Application-Specific Instruction-Set Processors
Journal of Signal Processing Systems
Programmable and Scalable Architecture for Graphics Processing Units
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Resource conflict detection in simulation of function unit pipelines
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Parallel memory architecture for TTA processor
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Domain specific architecture for next generation wireless communication
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic code generation on a MOVE processor using Cartesian genetic programming
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Low-Power Application-Specific Processor for FFT Computations
Journal of Signal Processing Systems
Exploring online synthesis for CGRAs with specialized operator sets
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
A heterogeneous embedded MPSoC for multimedia applications
HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
MOVE processors that self-replicate and differentiate
BioADIT'06 Proceedings of the Second international conference on Biologically Inspired Approaches to Advanced Information Technology
Formal specification of a protocol processor
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Tuning a protocol processor architecture towards DSP operations
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Hardware cost estimation for application-specific processor design
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A vector approach to cryptography implementation
DRMTICS'05 Proceedings of the First international conference on Digital Rights Management: technologies, Issues, Challenges and Systems
Low-power, high-performance TTA processor for 1024-point fast fourier transform
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Software pipelining support for transport triggered architecture processors
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Effects of program compression
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Architecture Optimization of Application-Specific Implicit Instructions
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
Template vertical dictionary-based program compression scheme on the TTA
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Design of a low-power embedded processor architecture using asynchronous function units
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Scheduling for register file energy minimization in explicit datapath architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Towards Generic Embedded Multiprocessing for RVC-CAL Dataflow Programs
Journal of Signal Processing Systems
Design of a transport triggered vector processor for turbo decoding
Analog Integrated Circuits and Signal Processing
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From the Publisher:The market for single chip microprocessors is huge and their performance continues to increase, driven by the on-going demand for more powerful applications, particularly in the control and signal processing domains. This work introduces a new type of computer architecture, the transport triggered architecture (TTA), designed to alleviate delay problems in existing instruction-level parallel architectures.