A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning
EURO-DAC '94 Proceedings of the conference on European design automation
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware/software partitioning with integrated hardware design space exploration
Proceedings of the conference on Design, automation and test in Europe
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessor Architectures: From VLIW to Tta
Microprocessor Architectures: From VLIW to Tta
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Transport-Triggering versus Operation-Triggering
CC '94 Proceedings of the 5th International Conference on Compiler Construction
On the hardware-software partitioning problem: System modeling and partitioning techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Process Partitioning for Distributed Embedded Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Move Processor for Bio-Inspired Systems
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RRES: a novel approach to the partitioning problem for a typical subset of system graphs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
A Hardware-Software Design Framework for Distributed Cellular Computing
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
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In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high level language our algorithm determines, using a dynamically-weighted fitness function, the most interesting code parts of the program to be implemented in hardware, given a limited amount of resources, in order to achieve the greatest overall execution speedup. The novelty of our approach resides in the tremendous reduction of the search space obtained by specific optimizations passes that are conducted on each generation. Moreover, by considering different granularities during the evolution process, very fast and effective convergence (in the order of a few seconds) can thus be attained. The partitioning obtained can then be used to build the different functional units of a processor well suited for a large customization, thanks to its architecture that uses only one instruction, Move.