Register file port requirements of transport triggered architectures
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Partitioned register file for TTAs
Proceedings of the 28th annual international symposium on Microarchitecture
Making graphs reducible with controlled node splitting
ACM Transactions on Programming Languages and Systems (TOPLAS)
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Design flow for hardware/software cosynthesis of a video compression system
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
A dynamically constrained genetic algorithm for hardware-software partitioning
Proceedings of the 8th annual conference on Genetic and evolutionary computation
A Hardware-Software Design Framework for Distributed Cellular Computing
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Parallel simulation of chip-multiprocessor by using multi-threading
AsiaMS '07 Proceedings of the IASTED Asian Conference on Modelling and Simulation
The research of an embedded processor element for multimedia domain
MCAM'07 Proceedings of the 2007 international conference on Multimedia content analysis and mining
Triggered instructions: a control paradigm for spatially-programmed architectures
Proceedings of the 40th Annual International Symposium on Computer Architecture
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