Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
MOVE: a framework for high-performance processor design
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Partitioned register files for VLIWs: a preliminary analysis of tradeoffs
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
MOVE32INT, a sea of gates realization of a high performance transport triggered architecture
EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications
Register allocation via graph coloring
Register allocation via graph coloring
Instruction-level experimental evaluation of the multiflow TRACE 14/300 VLIW computer
The Journal of Supercomputing - Special issue on instruction-level parallelism
Register file port requirements of transport triggered architectures
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Transport-Triggering versus Operation-Triggering
CC '94 Proceedings of the 5th International Conference on Compiler Construction
Design space exploration algorithm for heterogeneous multi-processor embedded system design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Software-Directed Register Deallocation for Simultaneous Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Computers
Reducing the complexity of the register file in dynamic superscalar processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Inter-Cluster Communication Models for Clustered VLIW Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Partitioned Schedules for Clustered VLIW Architectures
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Cluster assignment of global values for clustered VLIW processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
IEEE Transactions on Parallel and Distributed Systems
Very wide register: an asymmetric register file organization for low power embedded processors
Proceedings of the conference on Design, automation and test in Europe
Automatic volume management for programmable microfluidics
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Register Bank Assignment for Spatially Partitioned Processors
Languages and Compilers for Parallel Computing
Efficient compilation for queue size constrained queue processors
Parallel Computing
A Multi-Shared Register File Structure for VLIW Processors
Journal of Signal Processing Systems
The Journal of Supercomputing
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