Hierarchical registers for scientific computers
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Partitioned register files for VLIWs: a preliminary analysis of tradeoffs
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A study of partitioned vector register files
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Multirate systems and filter banks
Multirate systems and filter banks
The anatomy of the register file in a multiscalar processor
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Partitioned register file for TTAs
Proceedings of the 28th annual international symposium on Microarchitecture
The energy complexity of register files
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Communications of the ACM - Special issue on computer architecture
Modulo scheduling with integrated register spilling for clustered VLIW architectures
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
IEEE Micro
A Register File Architecture and Compilation Scheme for Clustered ILP Processors
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
The Mpact media processor redefines the multimedia PC
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Inter-Cluster Communication Models for Clustered VLIW Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Hierarchical Clustered Register File Organization for VLIW Processors
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Programmable Stream Processors
Computer
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
The energy efficiency of CMP vs. SMT for multimedia workloads
Proceedings of the 18th annual international conference on Supercomputing
A new register file access architecture for software pipelining in VLIW processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low power synthesizable register files for processor and IP cores
Integration, the VLSI Journal - Special issue: Low-power design techniques
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
RAPANUI: rapid prototyping for media processor architecture exploration
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A survey of media processing approaches
IEEE Transactions on Circuits and Systems for Video Technology
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The available instruction level parallelism allowed by current register file organizations is not always fully exploited by media processors when running a multimedia application. This paper introduces a novel register file organization, called multi-shared register file, that eliminates this superfluous instruction scheduling flexibility by reducing the number of read and write ports and partitioning the register file in a special ring structure. A parameterized generic VLIW architecture is used to explore different configurations of our proposed register file structure in terms of estimated silicon area, minimum clock period, estimated power consumption, and multimedia task processing performance. Moreover, a metric highly related to multimedia applications is introduced to study trade-offs between hardware cost and performance. The results show that by substituting a monolithic register file with an equivalent multi-shared register file, the estimated area and the power consumption are considerably reduced at the cost of a negligible performance degradation.