The anatomy of the register file in a multiscalar processor

Authors:
Scott E. Breach;T. N. Vijaykumar;Gurindar S. Sohi
Affiliations:
Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI;Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI;Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI
Venue:
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Year:
1994

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Abstract

This paper presents the operation of the register file in the Multiscalar architecture. The register file provides the appearance of a logically centralized register file, yet is implemented as physically decentralized register files, queues, and control logic in a Multiscalar processor. We address the key issues of storage, communication, and synchronization required for successful design and discuss the complications that arise in the face of speculation. In particular, the hardware required to implement the register file is detailed, and software support to streamline the operation of the register file is described. Illustrative examples detailing important aspects of the operation of the register file and an evaluation of its effectiveness are provided.