Multiscalar processors

Authors:
Gurindar S. Sohi;Scott E. Breach;T. N. Vijaykumar
Affiliations:
Computer Sciences Department, University of Wisconsin-Madison, Madison, WI;Computer Sciences Department, University of Wisconsin-Madison, Madison, WI;Computer Sciences Department, University of Wisconsin-Madison, Madison, WI
Venue:
25 years of the international symposia on Computer architecture (selected papers)
Year:
1998

Highly concurrent scalar processing

ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
The expandable split window paradigm for exploiting fine-grain parallelsim

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Effective compiler support for predicated execution using the hyperblock

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A comparison of dynamic branch predictors that use two levels of branch history

ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Guarded execution and branch prediction in dynamic ILP processors

ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
The anatomy of the register file in a multiscalar processor

MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
The multiscalar architecture

The multiscalar architecture
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References

IEEE Transactions on Computers
Superblock formation using static program analysis

MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
The impact of synchronization and granularity on parallel systems

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Look-Ahead Processors

ACM Computing Surveys (CSUR)

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