A Chip-Multiprocessor Architecture with Speculative Multithreading

  • Authors:

  • Venkata Krishnan;Josep Torrellas

  • Affiliations:

  • Compaq Computer Corp., Shrewsbury, MA;Univ. of Illinois at Urbana-Champaign, Urbana

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1999

Quantified Score

Hi-index 14.98

Visualization

Abstract

Much emphasis is now placed on chip-multiprocessor (CMP) architectures for exploiting thread-level parallelism in an application. In such architectures, speculation may be employed to execute applications that cannot be parallelized statically. In this paper, we present an efficient CMP architecture for speculative execution of sequential binaries without source recompilation. We present the software support that enables identification of threads from a sequential binary. The hardware includes a memory disambiguation mechanism that enables the detection of interthread memory dependence violations during speculative execution. This hardware is different from past proposals in that it does not rely on a snoopy-based cache-coherence protocol. Instead, it uses an approach similar to a directory-based scheme. Furthermore, the architecture includes a simple and efficient hardware mechanism to enable register-level communication between on-chip processors. Evaluation of this software-hardware approach shows that it is quite effective in achieving high performance when running sequential binaries.