Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor

  • Authors:

  • Jiwei Lu;Abhinav Das;Wei-Chung Hsu;Khoa Nguyen;Santosh G. Abraham

  • Affiliations:

  • University of Minnesota, Twin Cities;University of Minnesota, Twin Cities;University of Minnesota, Twin Cities;Sun Microsystems Inc.;Sun Microsystems Inc.

  • Venue:
  • Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2005

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Abstract

Data prefetching via helper threading has been extensively investigated on Simultaneous Multi- Threading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly large cache latency can be hidden by helper threads at runtime, most techniques rely on hardware support to reduce context switch overhead between the main thread and helper thread as well as rely on static profile feedback to construct the help thread code. This paper develops a new solution by exploiting helper threaded prefetching through dynamic optimization on the latest UltraSPARC Chip-Multiprocessing (CMP) processor. Our experiments show that by utilizing the otherwise idle processor core, a single user-level helper thread is sufficient to improve the runtime performance of the main thread without triggering multiple thread slices. Moreover, since the multiple cores are physically decoupled in the CMP, contention introduced by helper threading is minimal. This paper also discusses several key technical challenges of building a lightweight dynamic optimization/software scouting system on the UltraSPARC/Solaris platform.