on Parallel MIMD computation: HEP supercomputer and its applications
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
ICS '90 Proceedings of the 4th international conference on Supercomputing
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Java Virtual Machine Specification
Java Virtual Machine Specification
The Java Language Specification
The Java Language Specification
The SAGE graphics architecture
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
Tracking down software bugs using automatic anomaly detection
Proceedings of the 24th International Conference on Software Engineering
Speculative Multithreaded Processors
Computer
Computer
A survey of processors with explicit multithreading
ACM Computing Surveys (CSUR)
Efficient Interconnects for Clustered Microarchitectures
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Overcoming the limitations of conventional vector processors
Proceedings of the 30th annual international symposium on Computer architecture
Effectively sharing a cache among threads
Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures
A VLIW low power Java processor for embedded applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Managing Wire Delay in Large Chip-Multiprocessor Caches
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
High-Performance Throughput Computing
IEEE Micro
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
SableSpMT: a software framework for analysing speculative multithreading in Java
PASTE '05 Proceedings of the 6th ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
Energy-Efficient Thread-Level Speculation
IEEE Micro
SCMP: a single-chip message-passing parallel computer
The Journal of Supercomputing - Special issue: Parallel and distributed processing and applications
Constructing Virtual Architectures on a Tiled Processor
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TMA: a trap-based memory architecture
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Exploiting an abstract-machine-based framework in the design of a Java ILP processor
Journal of Systems Architecture: the EUROMICRO Journal
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A Multi-Shared Register File Structure for VLIW Processors
Journal of Signal Processing Systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
RIMP: runtime implicit predication
APPT'05 Proceedings of the 6th international conference on Advanced Parallel Processing Technologies
SARA: combining stack allocation and register allocation
CC'06 Proceedings of the 15th international conference on Compiler Construction
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The MAJC(tm) microprocessor architecture was developed by Sun Microsystems to address the extreme computation requirements needed by the emerging world of broadband services. Application performance is reached by exploiting parallelism at multiple levels. First and foremost, the architecture is inherently multithreaded. The ISA supports vertical multithreading, speculative multithreading and chip multiprocessors. Secondly, the MAJC VLIW architecture is capable of advanced speculation and predication. Finally, the architecture is heavily SIMD and treats all data types similarly (unified register file, unified execution resources, etc.).