ACM Computing Surveys (CSUR)
DAISY: dynamic compilation for 100% architectural compatibility
Proceedings of the 24th annual international symposium on Computer architecture
The Jalapeño dynamic optimizing compiler for Java
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
Allowing for ILP in an embedded Java processor
Proceedings of the 27th annual international symposium on Computer architecture
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Data-Driven and Demand-Driven Computer Architecture
ACM Computing Surveys (CSUR)
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation
IEEE Transactions on Computers - Special issue on the parallel architecture and compilation techniques conference
An analytical POC stack operations folding for continuous and discontinuous Java bytecodes
Journal of Systems Architecture: the EUROMICRO Journal
Instruction Folding in Java Processor
ICPADS '97 Proceedings of the 1997 International Conference on Parallel and Distributed Systems
Efficient JavaVM Just-in-Time Compilation
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
LaTTe: A Java VM Just-in-Time Compiler with Fast and Efficient Register Allocation
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
DELFT-JAVA Link Translation Buffer
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
A VLIW low power Java processor for embedded applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Exploiting an abstract-machine-based framework in the design of a Java ILP processor
Journal of Systems Architecture: the EUROMICRO Journal
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To design a Java processor with traditional modern processor architecture, the Instruction Level Parallelism (ILP) is not readily exploitable due to stack operands dependencies. This paper presents a dataflow-based instruction tagging scheme. With instruction tagging, the independent bytecode instruction groups with stack dependences are identified. The different bytecode instruction group can be executed in parallel because there are no stack dependences among them. With the instruction tagging scheme, we propose a tag-based multiissue semi-in-order (TMSI) Java processor. The processor takes advantage of instruction-tagging and stack-folding to generate the tagged register-based instructions. When the tagged instructions are ready, they are bundled out-of-order depending on data availability to form VLIW-like instruction words and issued in-order. To achieve high performance, a VLIW engine is employed. We have conducted some experiments in our TMSI simulation environment using SPECjvm98 and Linpack workload. The results indicate that the proposed processor has good performance gain.