ACM Computing Surveys (CSUR)
Transputer instruction set: a compiler writer's guide
Transputer instruction set: a compiler writer's guide
DAISY: dynamic compilation for 100% architectural compatibility
Proceedings of the 24th annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The Jalapeño dynamic optimizing compiler for Java
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
Allowing for ILP in an embedded Java processor
Proceedings of the 27th annual international symposium on Computer architecture
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Abstract machines for programming language implementation
Future Generation Computer Systems
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation
IEEE Transactions on Computers - Special issue on the parallel architecture and compilation techniques conference
Java Virtual Machine Specification
Java Virtual Machine Specification
An analytical POC stack operations folding for continuous and discontinuous Java bytecodes
Journal of Systems Architecture: the EUROMICRO Journal
Instruction Folding in Java Processor
ICPADS '97 Proceedings of the 1997 International Conference on Parallel and Distributed Systems
Efficient JavaVM Just-in-Time Compilation
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
LaTTe: A Java VM Just-in-Time Compiler with Fast and Efficient Register Allocation
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
DELFT-JAVA Link Translation Buffer
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
A VLIW low power Java processor for embedded applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
A cache based stack folding technique for high performance Java processors
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Consumer Electronics
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Abstract machines bridge the gap between the high-level of programming languages and the low-level mechanisms of a real machine. The paper proposed a general abstract-machine-based framework (AMBF) to build instruction level parallelism processors using the instruction tagging technique. The constructed processor may accept code written in any (abstract or real) machine instruction set, and produce tagged machine code after data conflicts are resolved. This requires the construction of a tagging unit which emulates the sequential execution of the program using tags rather than actual values. The paper presents a Java ILP processor by using the proposed framework. The Java processor takes advantage of the tagging unit to dynamically translate Java bytecode instructions to RISC-like tag-based instructions to facilitate the use of a general-purpose RISC core and enable the exploitation of instruction level parallelism. We detailed the Java ILP processor architecture and the design issues. Benchmarking of the Java processor using SpecJVM98 and Linpack has shown the overall ILP speedup improvement between 78% and 173%.