Performance comparison of ILP machines with cycle time evaluation
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
DAISY: dynamic compilation for 100% architectural compatibility
Proceedings of the 24th annual international symposium on Computer architecture
Abstract machines for programming language implementation
Future Generation Computer Systems
Java Virtual Machine Specification
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An EPIC Processor with Pending Functional Units
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
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ICPADS '97 Proceedings of the 1997 International Conference on Parallel and Distributed Systems
Banked multiported register files for high-frequency superscalar microprocessors
Proceedings of the 30th annual international symposium on Computer architecture
Exploiting an abstract-machine-based framework in the design of a Java ILP processor
Journal of Systems Architecture: the EUROMICRO Journal
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Abstract machines bridge the gap between a programming language and real machines. This paper proposes a general purpose tagged execution framework that may be used to construct a CPU. The CPU may accept code written in any (abstract or real) machine instruction set, and produce tagged machine code after data conflicts are resolved. This requires the construction of a tagging unit, which emulates the sequential execution of the program using tags rather than actual values. The tagged instructions are then sent to an execution engine that maps tags to values as they become available and sends ready-to-execute instructions to arithmetic units. The process of mapping tag to value may be performed using the Tomasulo scheme, or a register scheme with the result of instructions going to registers specified by their destination tags, and waiting instructions receiving operands from registers specified by their source tags.The tagged execution framework is suitable for any instruction architecture from RISC machines to stack machines. We will illustrate with an example of a Java ILP processor using a VLIW execution engine. Some related implementing issues are discussed.