Hardware support for large atomic units in dynamically scheduled machines
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
An architectural framework for migration from CISC to higher performance platforms
ICS '92 Proceedings of the 6th international conference on Supercomputing
Sentinel scheduling for VLIW and superscalar processors
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Communications of the ACM
A fill-unit approach to multiple instruction issue
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures
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Fast, effective dynamic compilation
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Trace cache: a low latency approach to high bandwidth instruction fetching
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Dynamically scheduled VLIW processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Exploiting instruction level parallelism in processors by caching scheduled groups
Proceedings of the 24th annual international symposium on Computer architecture
Shade: A Fast Instruction Set Simulator for Execution Profiling
Shade: A Fast Instruction Set Simulator for Execution Profiling
Disco: running commodity operating systems on scalable multiprocessors
ACM Transactions on Computer Systems (TOCS)
System support for automatic profiling and optimization
Proceedings of the sixteenth ACM symposium on Operating systems principles
Disco: running commodity operating systems on scalable multiprocessors
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Evaluation of scheduling techniques on a SPARC-based VLIW testbed
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Initial results on the performance and cost of vector microprocessors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Optimizations and oracle parallelism with dynamic translation
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Binary translation and architecture convergence issues for IBM system/390
Proceedings of the 14th international conference on Supercomputing
A hardware mechanism for dynamic extraction and relayout of program hot spots
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Proceedings of the 27th annual international symposium on Computer architecture
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Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Overcoming the challenges to feedback-directed optimization (Keynote Talk)
DYNAMO '00 Proceedings of the ACM SIGPLAN workshop on Dynamic and adaptive compilation and optimization
OS and compiler considerations in the design of the IA-64 architecture
ACM SIGPLAN Notices
Exploring the Interaction between Java's Implicitly Thrown Exceptions and Instruction Scheduling
International Journal of Parallel Programming
OS and compiler considerations in the design of the IA-64 architecture
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Rapid profiling via stratified sampling
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Managing multi-configuration hardware via dynamic working set analysis
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Performance characterization of a hardware mechanism for dynamic optimization
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Efficient static single assignment form for predication
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Instruction Level Distributed Processing
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Instruction Scheduling in the Presence of Java's Runtime Exceptions
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Optimizing Java Programs in the Presence of Exceptions
ECOOP '00 Proceedings of the 14th European Conference on Object-Oriented Programming
Instruction Level Distributed Processing: Adapting to Future Technology
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
Execution-Based Scheduling for VLIW Architectures
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
A New Facility for Dynamic Control of Program Execution: DELI
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Precise Exception Semantics in Dynamic Compilation
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Eliminating Exception Constraints of Java Programs for IA-64
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Dynamic compilation for energy adaptation
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DELI: a new run-time control point
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Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Retargetable and reconfigurable software dynamic translation
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An infrastructure for adaptive dynamic optimization
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Continuous program optimization: A case study
ACM Transactions on Programming Languages and Systems (TOPLAS)
Selecting long atomic traces for high coverage
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Dynamic Optimization of Micro-Operations
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A brief history of just-in-time
ACM Computing Surveys (CSUR)
Dynamic native optimization of interpreters
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DISE: a programmable macro engine for customizing applications
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LLVA: A Low-level Virtual Instruction Set Architecture
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Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture
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The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators
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Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems
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VHC: Quickly Building an Optimizer for Complex Embedded Architectures
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LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
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Power Awareness through Selective Dynamically Optimized Traces
Proceedings of the 31st annual international symposium on Computer architecture
Jazzing up JVMs with off-line profile data: does it pay?
ACM SIGPLAN Notices
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
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Effective Adaptive Computing Environment Management via Dynamic Optimization
Proceedings of the international symposium on Code generation and optimization
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Application of Binary Translation to Java Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Module-aware translation for real-life desktop applications
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Planning for code buffer management in distributed virtual execution environments
Proceedings of the 1st ACM/USENIX international conference on Virtual execution environments
SESS '05 Proceedings of the 2005 workshop on Software engineering for secure systems—building trustworthy applications
Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware
IEEE Transactions on Computers
Tdb: a source-level debugger for dynamically translated programs
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Low overhead program monitoring and profiling
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Reducing dynamic compilation overhead by overlapping compilation and execution
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A Cross-Architectural Interface for Code Cache Manipulation
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Thread-Shared Software Code Caches
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Constructing Virtual Architectures on a Tiled Processor
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Optimizing Dynamic Binary Translation for SIMD Instructions
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Dynamic parallelization and mapping of binary executables on hierarchical platforms
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Evaluating fragment construction policies for SDT systems
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Reducing Startup Time in Co-Designed Virtual Machines
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Decomposing the load-store queue by function for power reduction and scalability
IBM Journal of Research and Development
Compile-time planning for overhead reduction in software dynamic translators
International Journal of Parallel Programming - Special issue: The next generation software program
Branch predictor guided instruction decoding
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Managing bounded code caches in dynamic binary optimization systems
ACM Transactions on Architecture and Code Optimization (TACO)
Global instruction scheduling in dynamic compilation for embedded systems
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
Software-based instruction caching for embedded processors
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A dynamic binary instrumentation engine for the ARM architecture
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Effective management of multiple configurable units using dynamic optimization
ACM Transactions on Architecture and Code Optimization (TACO)
HDTrans: an open source, low-level dynamic instrumentation system
Proceedings of the 2nd international conference on Virtual execution environments
JIST: Just-In-Time scheduling translation for parallel processors
Scientific Programming
An intra-task dvfs technique based on statistical analysis of hardware events
Proceedings of the 4th international conference on Computing frontiers
Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems
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Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications
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SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance
Proceedings of the International Symposium on Code Generation and Optimization
Metadata driven memory optimizations in dynamic binary translator
Proceedings of the 3rd international conference on Virtual execution environments
Parallelization of IBM mambo system simulator in functional modes
ACM SIGOPS Operating Systems Review
Process-shared and persistent code caches
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PEAK—a fast and effective performance tuning system via compiler optimization orchestration
ACM Transactions on Programming Languages and Systems (TOPLAS)
Pipa: pipelined profiling and analysis on multi-core systems
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
VEAL: Virtualized Execution Accelerator for Loops
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Exploiting an abstract-machine-based framework in the design of a Java ILP processor
Journal of Systems Architecture: the EUROMICRO Journal
Mostly static program partitioning of binary executables
ACM Transactions on Programming Languages and Systems (TOPLAS)
Precise simulation of interrupts using a rollback mechanism
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
Using program metadata to support SDT in object-oriented applications
Proceedings of the 4th workshop on the Implementation, Compilation, Optimization of Object-Oriented Languages and Programming Systems
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A transformational approach to binary translation of delayed branches with applications to SPARC® and PA-RISC instructions sets
A cross-layer approach to heterogeneity and reliability
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Reducing exit stub memory consumption in code caches
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
The design and implementation of the DVS based dynamic compiler for power reduction
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Efficient binary translation system with low hardware cost
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Binary translation using peephole superoptimizers
OSDI'08 Proceedings of the 8th USENIX conference on Operating systems design and implementation
PiPA: Pipelined profiling and analysis on multicore systems
ACM Transactions on Architecture and Code Optimization (TACO)
DisIRer: Converting a retargetable compiler into a multiplatform binary translator
ACM Transactions on Architecture and Code Optimization (TACO)
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Efficient and effective misaligned data access handling in a dynamic binary translation system
ACM Transactions on Architecture and Code Optimization (TACO)
Evaluating indirect branch handling mechanisms in software dynamic translation systems
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Dynamo: a transparent dynamic optimization system
ACM SIGPLAN Notices
SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion
Proceedings of the 8th ACM International Conference on Computing Frontiers
A novel chaining approach to indirect control transfer instructions
ARES'11 Proceedings of the IFIP WG 8.4/8.9 international cross domain conference on Availability, reliability and security for business, enterprise and health information systems
An energy-aware whole-system dynamic emulator – skyeye
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
Transparent dynamic instrumentation
VEE '12 Proceedings of the 8th ACM SIGPLAN/SIGOPS conference on Virtual Execution Environments
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
VEE '12 Proceedings of the 8th ACM SIGPLAN/SIGOPS conference on Virtual Execution Environments
PARROT: power awareness through selective dynamically optimized traces
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Selective runtime memory disambiguation in a dynamic binary translator
CC'06 Proceedings of the 15th international conference on Compiler Construction
Trace execution automata in dynamic binary translation
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
ISAMAP: instruction mapping driven by dynamic binary translation
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
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SINOF: A dynamic-static combined framework for dynamic binary translation
Journal of Systems Architecture: the EUROMICRO Journal
Memory optimization of dynamic binary translators for embedded systems
ACM Transactions on Architecture and Code Optimization (TACO)
Optimizing indirect branches in a system-level dynamic binary translator
Proceedings of the 5th Annual International Systems and Storage Conference
Fast simulation of systems embedding VLIW processors
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Bringing Virtualization to the x86 Architecture with the Original VMware Workstation
ACM Transactions on Computer Systems (TOCS)
StarDBT: an efficient multi-platform dynamic binary translation system
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Discerning the dominant out-of-order performance advantage: is it speculation or dynamism?
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
TSO_ATOMICITY: efficient hardware primitive for TSO-preserving region optimizations
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the ACM International Conference on Computing Frontiers
Warm-Up Simulation Methodology for HW/SW Co-Designed Processors
Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization
JIT technology with C/C++: Feedback-directed dynamic recompilation for statically compiled languages
ACM Transactions on Architecture and Code Optimization (TACO)
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Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impediment to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call DAISY (Dynamically Architected Instruction Set from Yorktown). DAISY is specifically intended to emulate existing architectures, so that all existing software for an old architecture (including operating system kernel code) runs without changes on the VLIW. Each time a new fragment of code is executed for the first time, the code is translated to VLIW primitives, parallelized and saved in a portion of main memory not visible to the old architecture, by a Virtual Machine Monitor (software) residing in read only memory. Subsequent executions of the same fragment do not require a translation (unless cast out). We discuss the architectural requirements for such a VLIW, to deal with issues including self-modifying code, precise exceptions, and aggressive reordering of memory references in the presence of strong MP consistency and memory mapped I/O. We have implemented the dynamic parallelization algorithms for the PowerPC architecture. The initial results show high degrees of instruction level parallelism with reasonable translation overhead and memory usage.