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Efficient superscalar performance through boosting
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Communications of the ACM
Shade: a fast instruction-set simulator for execution profiling
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Dynamic memory disambiguation using the memory conflict buffer
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
DAISY: dynamic compilation for 100% architectural compatibility
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The Jalapeño dynamic optimizing compiler for Java
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Dynamo: a transparent dynamic optimization system
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Dynamic Binary Translation and Optimization
IEEE Transactions on Computers
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Precise Exception Semantics in Dynamic Compilation
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The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators
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VHC: Quickly Building an Optimizer for Complex Embedded Architectures
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Effective Adaptive Computing Environment Management via Dynamic Optimization
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Maintaining Consistency and Bounding Capacity of Software Code Caches
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Module-aware translation for real-life desktop applications
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Instrumentation in software dynamic translators for self-managed systems
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Compile-time planning for overhead reduction in software dynamic translators
International Journal of Parallel Programming - Special issue: The next generation software program
Branch predictor guided instruction decoding
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t-kernel: providing reliable OS support to wireless sensor networks
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Journal of Systems Architecture: the EUROMICRO Journal
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VXA: a virtual architecture for durable compressed archives
FAST'05 Proceedings of the 4th conference on USENIX Conference on File and Storage Technologies - Volume 4
Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications
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Contention-aware scheduler: unlocking execution parallelism in multithreaded java programs
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An Evaluation of Misaligned Data Access Handling Mechanisms in Dynamic Binary Translation Systems
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A highly flexible, parallel virtual machine: design and experience of ILDJIT
Software—Practice & Experience
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Optimized register renaming scheme for stack-based x86 operations
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
TAO: two-level atomicity for dynamic binary optimizations
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
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Proceedings of the Workshop on Binary Instrumentation and Applications
Reusing cached schedules in an out-of-order processor with in-order issue logic
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Efficient binary translation system with low hardware cost
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems
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SPUR: a trace-based JIT compiler for CIL
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CoDBT: A multi-source dynamic binary translator using hardware-software collaborative techniques
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DisIRer: Converting a retargetable compiler into a multiplatform binary translator
ACM Transactions on Architecture and Code Optimization (TACO)
Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures
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Efficient and effective misaligned data access handling in a dynamic binary translation system
ACM Transactions on Architecture and Code Optimization (TACO)
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ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
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SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion
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A novel chaining approach to indirect control transfer instructions
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Trace-Based data cache leakage reduction at link time
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Trace-Based runtime instruction rescheduling for architecture extension
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
VEE '12 Proceedings of the 8th ACM SIGPLAN/SIGOPS conference on Virtual Execution Environments
Replacement attacks against VM-protected applications
VEE '12 Proceedings of the 8th ACM SIGPLAN/SIGOPS conference on Virtual Execution Environments
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Selective runtime memory disambiguation in a dynamic binary translator
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Trace execution automata in dynamic binary translation
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ISAMAP: instruction mapping driven by dynamic binary translation
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LAR-CC: Large atomic regions with conditional commits
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
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CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
Static analysis and compiler design for idempotent processing
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Speculative hardware/software co-designed floating-point multiply-add fusion
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ASC: automatically scalable computation
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CAeSaR: unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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Transmeta's Crusoe microprocessor is a full, system-level implementation of the x86 architecture, comprising a native VLIW microprocessor with a software layer, the Code Morphing Software (CMS), that combines an interpreter, dynamic binary translator, optimizer, and runtime system. In its general structure, CMS resembles other binary translation systems described in the literature, but it is unique in several respects. The wide range of PC workloads that CMS must handle gracefully in real-life operation, plus the need for full system-level x86 compatibility, expose several issues that have received little or no attention in previous literature, such as exceptions and interrupts, I/O, DMA, and self-modifying code. In this paper we discuss some of the challenges raised by these issues, and present the techniques developed in Crusoe and CMS to meet those challenges. The key to these solutions is the Crusoe paradigm of aggressive speculation, recovery to a consistent x86 state using unique hardware commit-and-rollback support, and adaptive retranslation when exceptions occur too often to be handled efficiently by interpretation.