Improving dynamic binary optimization through early-exit guided code region formation

  • Authors:

  • Chun-Chen Hsu;Pangfeng Liu;Jan-Jan Wu;Pen-Chung Yew;Ding-Yong Hong;Wei-Chung Hsu;Chien-Min Wang

  • Affiliations:

  • National Taiwan University, Taipei, Taiwan Roc;National Taiwan University, Taipei, Taiwan Roc;Academia Sinica, Taipei, Taiwan Roc;University of Minnesota, Twin Cities, MN, USA;Academia Sinica, Taipei, Taiwan Roc;National Chiao Tung University, Hsinchu, Taiwan Roc;Academia Sinica, Taipei, Taiwan Roc

  • Venue:
  • Proceedings of the 9th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments
  • Year:
  • 2013

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Abstract

Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces. In this paper, we propose a light-weight region formation technique called Early-Exit Guided Region Formation (EEG) to improve the quality of the formed traces/regions. It iteratively identifies and merges delinquent regions into larger code regions. We have implemented our EEG algorithm in two LLVM-based multi-threaded DBTs targeting ARM and IA32 instruction set architecture (ISA), respectively. Using SPEC CPU2006 benchmark suite with reference inputs, our results show that compared to an NET-variant currently used in QEMU, a state-of-the-art retargetable DBT, EEG can achieve a significant performance improvement of up to 72% (27% on average), and to 49% (23% on average) for IA32 and ARM, respectively.