FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

  • Authors:

  • Niket K. Choudhary;Salil V. Wadhavkar;Tanmay A. Shah;Hiran Mayukh;Jayneel Gandhi;Brandon H. Dwiel;Sandeep Navada;Hashem H. Najaf-abadi;Eric Rotenberg

  • Affiliations:

  • North Carolina State University, Raleigh, NC, USA;North Carolina State University, Raleigh, NC, USA;Intel Corporation, Hillsboro, OR, USA;University of Wisconsin - Madison, Madison, WI, USA;University of Wisconsin - Madison, Madison, WI, USA;North Carolina State University, Raleigh, NC, USA;North Carolina State University, Raleigh, NC, USA;Intel Corporation, Folsom, CA, USA;North Carolina State University, Raleigh, NC, USA

  • Venue:
  • Proceedings of the 38th annual international symposium on Computer architecture
  • Year:
  • 2011

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Abstract

A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-designed superscalar core types that can streamline the execution of diverse programs and program phases. No prior research has addressed the 'Achilles' heel of this paradigm: design and verification effort is multiplied by the number of different core types. This work frames superscalar processors in a canonical form, so that it becomes feasible to quickly design many cores that differ in the three major superscalar dimensions: superscalar width, pipeline depth, and sizes of structures for extracting instruction-level parallelism (ILP). From this idea, we develop a toolset, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template. The template defines canonical pipeline stages and interfaces among them. A Canonical Pipeline Stage Library (CPSL) provides many implementations of each canonical pipeline stage, that differ in their superscalar width and depth of sub-pipelining. An RTL generation tool uses the template and CPSL to automatically generate an overall core of desired configuration. Validation experiments are performed along three fronts to evaluate the quality of RTL designs generated by FabScalar: functional and performance (instructions-per-cycle (IPC)) validation, timing validation (cycle time), and confirmation of suitability for standard ASIC flows. With FabScalar, a chip with many different superscalar core types is conceivable.