The energy efficiency of CMP vs. SMT for multimedia workloads
Proceedings of the 18th annual international conference on Supercomputing
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Predictive technology model for nano-CMOS design exploration
ACM Journal on Emerging Technologies in Computing Systems (JETC)
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI Degradation: A Problem or a Scare?
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
NBTI aware workload balancing in multi-core systems
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Workload capacity considering NBTI degradation in multi-core systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
NBTI-aware power gating design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 38th annual international symposium on Computer architecture
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Negative-Bias Temperature Instability has become a serious reliability concern in modern processors design, and in the last decade many research effort has been spent in developing circuit-level and architecture-level strategies to mitigate the induced delay variation of nanoscale circuits. At the architecture level, work has been proposed to alleviate this by appropriate dynamic instruction schedulingntechniques. However, their benefit is bounded to the available redundancy, limiting their attractiveness for a cost-effective VLSI solution. This paper presents an in-depth analysis of a performance reliability trade-off FSM design, that is able to attain the desired level of reliability improvement according to the ILP performance constraints. Power-gating is used for aggressive NBTI restoration. Extensive experimental results show several performance reliability trade-off examples in a broad range of application scenarios.