NBTI aware workload balancing in multi-core systems

Authors:
Jin Sun;Avinash Kodi;Ahmed Louri;Janet M. Wang
Affiliations:
Department of Electrical and Computer Engineering, University of Arizona, 1230 E. Speedway, Tucson, 85721, USA;Department of Electrical and Computer Engineering, Russ College of Engineering and Technology, Ohio University, 322D Stocker Center, Athens, 45701, USA;Department of Electrical and Computer Engineering, University of Arizona, 1230 E. Speedway, Tucson, 85721, USA;Department of Electrical and Computer Engineering, University of Arizona, 1230 E. Speedway, Tucson, 85721, USA
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

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Abstract

As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such as Negative Bias Temperature Instability (NBTI). Unless this problem is addressed, chip multi-processor (CMP) systems face low yields and short mean-time-to-failure (MTTF). This paper proposes a new design framework for multi-core system that includes device wear-out impact. Based on device fractional NBTI model, we propose a new NBTI aware system workload model, and develop new dynamic tile partition (DTP) algorithm to balance workload among active cores while relaxing stressed ones. Experimental results on 64 cores show that by allowing a small number of cores (around 10%)to relax in a short time period (10 second), the proposed methodology improves CMP system yield. We use the percentage of core failure to represent the yield improvement. The new strategy improves the core failure number by 20 %, and extend MTTF by 30% with little degradation in performance (less than 6%).