NBTI mitigation in microprocessor designs

  • Authors:
  • Simone Corbetta;William Fornaciari

  • Affiliations:
  • Politecnico di Milano, Milano, Italy;Politecnico di Milano, Milano, Italy

  • Venue:
  • Proceedings of the great lakes symposium on VLSI
  • Year:
  • 2012

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Abstract

Negative-Bias Temperature Instability seriously affects nanoscale circuits reliability and performance. Continuous stress and increasing operating temperatures lead to device degradation and long-term system unavailability. The opportunity to optimize the duty-cycle of the stress/recovery phases to reduce Vth degradation leads to innovative research of reliability-oriented resources allocation at architectural level. This work explores the impact of different allocation strategies on the processor degradation, through a novel estimation methodology. Experimental results show that the proposed NBTI-aware allocation strategy can guarantee from 10% and up to 30% lower degradation compared to classical strategies, under different operating scenarios and under process variability.