Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Design Challenges of Technology Scaling
IEEE Micro
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
An Architectural Framework for Providing Reliability and Security Support
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Electronics beyond nano-scale CMOS
Proceedings of the 43rd annual Design Automation Conference
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
IEEE Design & Test
Reunion: Complexity-Effective Multicore Redundancy
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Configurable isolation: building high availability systems with commodity multi-core processors
Proceedings of the 34th annual international symposium on Computer architecture
Fault-tolerant typed assembly language
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
The visual vulnerability spectrum: characterizing architectural vulnerability for graphics hardware
GH '06 Proceedings of the 21st ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Proceedings of the 2008 international workshop on System level interconnect prediction
Reliability-aware design for nanometer-scale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Dependability, power, and performance trade-off on a multicore processor
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 5th conference on Computing frontiers
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
A temperature-aware virtual submesh allocation scheme for noc-based manycore chips
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
Proceedings of the conference on Design, automation and test in Europe
Globally optimized robust systems to overcome scaled CMOS reliability challenges
Proceedings of the conference on Design, automation and test in Europe
Software protection mechanisms for dependable systems
Proceedings of the conference on Design, automation and test in Europe
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
Reasoning about Control Flow in the Presence of Transient Faults
SAS '08 Proceedings of the 15th international symposium on Static Analysis
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
Phaser: phased methodology for modeling the system-level effects of soft errors
IBM Journal of Research and Development
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A framework for estimating NBTI degradation of microarchitectural components
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementing high availability memory with a duplication cache
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
The StageNet fabric for constructing resilient multicore systems
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Online circuit reliability monitoring
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Tolerating process variations in large, set-associative caches: The buddy cache
ACM Transactions on Architecture and Code Optimization (TACO)
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
AN-Encoding Compiler: Building Safety-Critical Systems with Commodity Hardware
SAFECOMP '09 Proceedings of the 28th International Conference on Computer Safety, Reliability, and Security
Architecture Design for Soft Errors
Architecture Design for Soft Errors
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
ESL power analysis of embedded processors for temperature and reliability estimations
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Design perspectives on 22nm CMOS and beyond
Proceedings of the 46th Annual Design Automation Conference
Vicis: a reliable network for unreliable silicon
Proceedings of the 46th Annual Design Automation Conference
System-level exploration of run-time clusterization for energy-efficient on-chip communication
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Variation-aware low-power synthesis methodology for fixed-point FIR filters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ZerehCache: armoring cache architectures in high defect density technologies
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
mSWAT: low-cost hardware fault detection and diagnosis for multicore systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Operating system scheduling for efficient online self-test in robust systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Post-fabrication measurement-driven oxide breakdown reliability prediction and management
Proceedings of the 2009 International Conference on Computer-Aided Design
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Speculation for Parallelizing Runtime Checks
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Parallelizing Software-Implemented Error Detection
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
International Journal of Parallel Programming
Shoestring: probabilistic soft error reliability on the cheap
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Impact of device variability in the communication structures for future synchronous SoC designs
SOC'09 Proceedings of the 11th international conference on System-on-chip
Energy-efficient redundant execution for chip multiprocessors
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Power-efficient, reliable microprocessor architectures: modeling and design methods
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
The salvage cache: a fault-tolerant cache architecture for next-generation memory technologies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Adaptive online testing for efficient hard fault detection
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Interconnection alternatives for hierarchical monitoring communication in parallel SoCs
Microprocessors & Microsystems
Necromancer: enhancing system throughput by animating dead cores
Proceedings of the 37th annual international symposium on Computer architecture
Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A table-based approach to study the impact of process variations on finfet circuit performance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Scalable thread scheduling and global power management for heterogeneous many-core architectures
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
A realistic evaluation of memory hardware errors and software system susceptibility
USENIXATC'10 Proceedings of the 2010 USENIX conference on USENIX annual technical conference
Economic analysis of testing homogeneous Manycore chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
AgeSim: a simulation framework for evaluating the lifetime reliability of processor-based SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Aging-resilient design of pipelined architectures using novel detection and correction circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Process variation and temperature-aware reliability management
Proceedings of the Conference on Design, Automation and Test in Europe
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Vision for cross-layer optimization to address the dual challenges of energy and reliability
Proceedings of the Conference on Design, Automation and Test in Europe
Design techniques for cross-layer resilience
Proceedings of the Conference on Design, Automation and Test in Europe
Cross-layer resilience challenges: metrics and optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Multiplexed redundant execution: a technique for efficient fault tolerance in chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
Proceedings of the Conference on Design, Automation and Test in Europe
A self-adaptive system architecture to address transistor aging
Proceedings of the Conference on Design, Automation and Test in Europe
Masking timing errors on speed-paths in logic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Configurable links for runtime adaptive on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
Improving yield and reliability of chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
A unified online fault detection scheme via checking of stability violation
Proceedings of the Conference on Design, Automation and Test in Europe
ANB- and ANBDmem-encoding: detecting hardware errors in software
SAFECOMP'10 Proceedings of the 29th international conference on Computer safety, reliability, and security
Benefits and barriers for probabilistic design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Erasing Core Boundaries for Robust and Configurable Performance
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Communications of the ACM
A fault-tolerant interconnect mechanism for NMR nanoarchitectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A resilient on-chip router design through data path salvaging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Scalable multi-input-multi-output queues with application to variation-tolerant architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems
ACM Transactions on Architecture and Code Optimization (TACO)
Resilience of mutual exclusion algorithms to transient memory faults
Proceedings of the 30th annual ACM SIGACT-SIGOPS symposium on Principles of distributed computing
Autonomous multi-processor-SoC optimization with distributed learning classifier systems XCS
Proceedings of the 8th ACM international conference on Autonomic computing
A distributed and topology-agnostic approach for on-line NoC testing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Sampling + DMR: practical and low-overhead permanent fault detection
Proceedings of the 38th annual international symposium on Computer architecture
Re-synthesis for cost-efficient circuit-level timing speculation
Proceedings of the 48th Design Automation Conference
Significance driven computation on next-generation unreliable platforms
Proceedings of the 48th Design Automation Conference
Customer-aware task allocation and scheduling for multi-mode MPSoCs
Proceedings of the 48th Design Automation Conference
In-field aging measurement and calibration for power-performance optimization
Proceedings of the 48th Design Automation Conference
Cost-effective safety and fault localization using distributed temporal redundancy
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Design and architectures for dependable embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Reliability analysis for MPSoCs with mixed-critical, hard real-time constraints
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FTI: high performance fault tolerance interface for hybrid systems
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Choose-your-own-adventure routing: Lightweight load-time defect avoidance
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Service based communication for MPSoC platform-SegBus
Microprocessors & Microsystems
ROBUST: a new self-healing fault-tolerant NoC router
Proceedings of the 4th International Workshop on Network on Chip Architectures
Cross-layer error resilience for robust systems
Proceedings of the International Conference on Computer-Aided Design
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Maestro: orchestrating lifetime reliability in chip multiprocessors
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
A case study on error resilient architectures for wireless communication
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
NBTI mitigation in microprocessor designs
Proceedings of the great lakes symposium on VLSI
NBTI effects on tree-like clock distribution networks
Proceedings of the great lakes symposium on VLSI
Benefits of selective packet discard in networks-on-chip
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the 9th conference on Computing Frontiers
Early prediction of NBTI effects using RTL source code analysis
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 26th ACM international conference on Supercomputing
Selectively fortifying reconfigurable computing device to achieve higher error resilience
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Proceedings of the 39th Annual International Symposium on Computer Architecture
A first-order mechanistic model for architectural vulnerability factor
Proceedings of the 39th Annual International Symposium on Computer Architecture
Viper: virtual pipelines for enhanced reliability
Proceedings of the 39th Annual International Symposium on Computer Architecture
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems
Journal of Electronic Testing: Theory and Applications
Operating system support for redundant multithreading
Proceedings of the tenth ACM international conference on Embedded software
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Who watches the watchmen? - protecting operating system reliability mechanisms
HotDep'12 Proceedings of the Eighth USENIX conference on Hot Topics in System Dependability
Accurate characterization of the variability in power consumption in modern mobile processors
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
A novel gate-level NBTI delay degradation model with stacking effect
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Software encoded processing: building dependable systems with commodity hardware
SAFECOMP'07 Proceedings of the 26th international conference on Computer Safety, Reliability, and Security
SAFECOMP'12 Proceedings of the 31st international conference on Computer Safety, Reliability, and Security
On logic synthesis for timing speculation
Proceedings of the International Conference on Computer-Aided Design
International Journal of Adaptive, Resilient and Autonomic Systems
Heuristic search for adaptive, defect-tolerant multiprocessor arrays
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Performance Analysis of On-Chip Communication Structures under Device Variability
International Journal of Embedded and Real-Time Communication Systems
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 7th International Conference on Body Area Networks
Holistic run-time parallelism management for time and energy efficiency
Proceedings of the 27th international ACM conference on International conference on supercomputing
A JVM for soft-error-prone embedded systems
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
Journal of Electronic Testing: Theory and Applications
A novel intermittent fault Markov model for deep sub-micron processors
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Combating NBTI-induced aging in data caches
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
AVICA: an access-time variation insensitive L1 cache architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Reliability analysis reloaded: how will we survive?
Proceedings of the Conference on Design, Automation and Test in Europe
Breaking the energy barrier in fault-tolerant caches for multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and analysis of fault-tolerant distributed memories for networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime resource allocation for software pipelines
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
On testing timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits
Proceedings of the 50th Annual Design Automation Conference
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware leakage power model extraction for system-level hierarchical power analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Low power aging-aware register file design by duty cycle balancing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A resilient architecture for low latency communication in shared-L1 processor clusters
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
CrashTest'ing SWAT: accurate, gate-level evaluation of symptom-based resiliency solutions
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Towards scalable arithmetic units with graceful degradation
ACM Transactions on Embedded Computing Systems (TECS)
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Detecting silent data corruption through data dynamic monitoring for scientific applications
Proceedings of the 19th ACM SIGPLAN symposium on Principles and practice of parallel programming
ArchOn: Architecture-open Resource-driven Cross-layer Modelling Framework
Proceedings of International Workshop on Engineering Simulations for Cyber-Physical Systems
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A low-power instruction replay mechanism for design of resilient microprocessors
ACM Transactions on Embedded Computing Systems (TECS)
ForTER: a forward error correction scheme for timing error resilience
Proceedings of the International Conference on Computer-Aided Design
Surviving sensor node failures by MMU-less incremental checkpointing
Journal of Systems and Software
DeSyRe: On-demand system reliability
Microprocessors & Microsystems
Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Unified reliability estimation and management of NoC based chip multiprocessors
Microprocessors & Microsystems
Supporting faulty banks in NUCA by NoC assisted remapping mechanisms
The Journal of Supercomputing
| Hi-index | 0.02 |
As technology scales, variability will continue to become worse. Random dopantfluctuations and sub-wavelength lithography will yield static variations, supply voltageand temperature variations will affect circuit performance and leakage power, soft-errorrates will continue to rise, and transistor aging will become worse. We discuss theseeffects and propose solutions to build reliable systems with billions of unreliablecomponents.