A novel intermittent fault Markov model for deep sub-micron processors

Authors:
Babak Saghaie;Roshan Ragel;Sri Parameswaran;Aleks Ignjatovic
Affiliations:
The University of New South Wales, Sydney, Australia;The University of Peradeniya, Peradeniya, Sri Lanka;The University of New South Wales, Sydney, Australia;The University of New South Wales, Sydney, Australia
Venue:
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Year:
2013

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Abstract

Intermittent faults (IF) in chips are becoming commonplace with the current technology trend and the process scaling. In this paper, we first modify the well known birth-death Markov model so that availability can be calculated. We then show that the standard birth-death Markov model does not capture IF correctly, and create a novel Markov model for intermittent faults that is derived from the specific nature of such faults. The proposed model, for the first time, differentiates risky and normal components and therefore does not waste processing time for unnecessary testing procedures. Consequently, the availability of processors with the proposed model increases significantly compared to the traditional model (from 0.90 to 0.99 with a typical parameter set). In addition, the proposed model facilitates parameter space exploration. Positive effects were observed with varying parameters such as error rate, recovery time and test program length. It was concluded that choice of right testing parameters are vital for gaining optimal system availability and the new model supports achieving the same.