A constraint-based solution for on-line testing of processors embedded in real-time applications
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Adaptive online testing for efficient hard fault detection
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Effective diagnostic pattern generation strategy for transition-delay faults in full-scan SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
A novel intermittent fault Markov model for deep sub-micron processors
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Low cost permanent fault detection using ultra-reduced instruction set co-processors
Proceedings of the Conference on Design, Automation and Test in Europe
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low-cost embedded systems with respect to permanent and intermittent operational faults. Such strategies are well suited to embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, information, software, or time-redundancy mechanisms. We first identify the stringent characteristics of a SBST program to be suitable for on-line periodic testing. Also, we study the probability for a SBST program to detect permanent and intermittent faults during on-line periodic testing. Then, we introduce a new SBST methodology with a new classification and test-priority scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for two pipeline reduced instruction set computers reduced instruction set processors of different architecture.