Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection

Authors:
Sébastien Sarrazin;Samuel Evain;Lirida Alves de Barros Naviner;Yannick Bonhomme;Valentin Gherman
Affiliations:
CEA, LIST, Gif sur Yvette CEDEX, France;CEA, LIST, Gif sur Yvette CEDEX, France;Telecom ParisTech, Paris CEDEX, France;CEA, LIST, Gif sur Yvette CEDEX, France;CEA, LIST, Gif sur Yvette CEDEX, France
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

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Abstract

This paper presents new scan solutions with low latency overhead and on-line monitoring support. Shadow flip-flops with scan design are associated to system flip-flops in order to (a) provide concurrent delay fault detection and (b) avoid the scan chain insertion of system flip-flops. A mixed scan architecture is proposed which involves flip-flops with shadow scan design at the end of timing-critical paths and flip-flops with standard scan at non-critical locations. In order to preserve system controllability during test, system flip-flops with shadow scan can be set in scan mode and selectively reset before switching to capture mode. It is shown that shadow scan design with asynchronous set and reset may have a lower latency overhead than standard scan design. A shadow scan solution is proposed which, in addition to concurrent delay fault detection, provides simultaneous scan and capture capability.