A Procedure for Selecting Diagnostic Tests
IEEE Transactions on Computers
Diagnosis of Single-Gate Failures in Combinational circuits
IEEE Transactions on Computers
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
A Method for the Design of Fault Detection Experiments
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Derivation of optimum test sequencies for sequential machines
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Ternary Scan Design for VLSI Testability
IEEE Transactions on Computers
Behavioral synthesis for testability
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ATPG for scan chain latches and flip-flops
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Modifying User-Defined Logic for Test Access to Embedded Cores
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Scan Encoded Test Pattern Generation for BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
IEEE Transactions on Computers
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Sequential Network Design Using Extra Inputs for Fault Detection
IEEE Transactions on Computers
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
Easily Testable Sequential Machines with Extra Inputs
IEEE Transactions on Computers
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Synthesis of reversible sequential elements
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Detectability of internal bridging faults in scan chains
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Design and verification of the IBM system z10 I/O subsystem chips
IBM Journal of Research and Development
Hybrid design for testability combining scan and clock line control and method for test generation
ITC'94 Proceedings of the 1994 international conference on Test
Using scan technology for debug and diagnostics in a workstation environment
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing
An analysis of the economics of self-test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Pseudo-exhaustive testing of sequential machines using signature analysis
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LSI logic testing: an overview
IEEE Transactions on Computers
TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead
Proceedings of the 48th Design Automation Conference
Post-silicon fault localisation using maximum satisfiability and backbones
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Lazy suspect-set computation: fault diagnosis for deep electrical bugs
Proceedings of the great lakes symposium on VLSI
nuTAB-BackSpace: rewriting to normalize non-determinism in post-silicon debug traces
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Formal Verification and Diagnosis of Combinational Circuit Designs with Propositional Logic
Fundamenta Informaticae
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 15.02 |
With the increasing complexity of logic that can be fabricated on a single large-scale integrated (LSI) circuit chip, there is a growing problem of checking the logical behavior of the chips at manufacture. The problem is particularly acute for sequential circuits, where there are difficulties in setting and checking the state of the system.