Pseudo-exhaustive testing of sequential machines using signature analysis

Authors:
Syed Zahoor Hassan;Edward J. McCluskey
Affiliations:
Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, California and Trilogy Systems Corporation, C ...;Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, California
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

A design for testability (DFT) structure for sequential machines is presented. This design has the following characteristics: it requires augmentation of sequential machines by addition of an extra input and some associated logic; the test sequence is the same for all machines with a given number of input combinations, states, and outputs; it uses signature analysis to compact the output response; fault diagnosis is possible by obtaining intermediate signatures; and it is suitable for built-in self-test (BIST). A systematic procedure for testing the sequential machines designed by this method is presented. The test length is also calculated. An example of a practical machine is used to illustrate the proposed scheme.