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Totally Preset Checking Experiments for Sequential Machines
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Asynchronous Sequential Machines Designed for Fault Detection
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Sequential Machine Identification
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Truth-Table Verification of an Iterative Logic Array
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This paper describes the design of experimental procedures for determining whether or not a sequential switching circuit is operating in accordance with a given state-table description. These procedures are particularly easy to apply when the given state table is reduced, strongly-connected, and has a distinguishing sequence, and when the actual circuit has no more states than the given table. They can also be extended to cover more general cases, although the resulting experiments are more cumbersome.