Selecting test sequences for partially-specified nondeterministic finite state machines
IWPTS '94 7th IFIP WG 6.1 international workshop on Protocol test systems
On Minimizing the Lengths of Checking Sequences
IEEE Transactions on Computers
Test Generation for Multiple State-Table Faults in Finite-State Machines
IEEE Transactions on Computers
Computer Networks
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Testing Enbredded Software
Reduced Length Checking Sequences
IEEE Transactions on Computers
IEEE Transactions on Software Engineering
Conformance Testing of Protocol Machines without Reset
Proceedings of the IFIP TC6/WG6.1 Thirteenth International Symposium on Protocol Specification, Testing and Verification XIII
Modeling basic LOTOS by FSMs for conformance testing
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Generating Tests for Control Portion of SDL Specifications
Proceedings of the IFIP TC6/WG6.1 Sixth International Workshop on Protocol Test systems VI
Confirming Configurations in EFSM Testing
IEEE Transactions on Software Engineering
Using a minimal number of resets when testing from a finite state machine
Information Processing Letters
Testing from a Nondeterministic Finite State Machine Using Adaptive State Counting
IEEE Transactions on Computers
A Method for the Design of Fault Detection Experiments
IEEE Transactions on Computers
IEEE Transactions on Computers
Testing Software Design Modeled by Finite-State Machines
IEEE Transactions on Software Engineering
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Test generation based on control and data dependencies within system specifications in SDL
Computer Communications
Using adaptive distinguishing sequences in checking sequence constructions
Proceedings of the 2008 ACM symposium on Applied computing
Generating Checking Sequences for Partial Reduced Finite State Machines
TestCom '08 / FATES '08 Proceedings of the 20th IFIP TC 6/WG 6.1 international conference on Testing of Software and Communicating Systems: 8th International Workshop
Using formal specifications to support testing
ACM Computing Surveys (CSUR)
Verdict functions in testing with a fault domain or test hypotheses
ACM Transactions on Software Engineering and Methodology (TOSEM)
Exploring alternatives for transition verification
Journal of Systems and Software
Estimating the feasibility of transition paths in extended finite state machines
Automated Software Engineering
Generating Reduced Tests for FSMs with Extra States
TESTCOM '09/FATES '09 Proceedings of the 21st IFIP WG 6.1 International Conference on Testing of Software and Communication Systems and 9th International FATES Workshop
Iterative execution-feedback model-directed GUI testing
Information and Software Technology
Generating a checking sequence with a minimum number of reset transitions
Automated Software Engineering
Checking experiments for stream X-machines
Theoretical Computer Science
Reaching and Distinguishing States of Distributed Systems
SIAM Journal on Computing
Using distinguishing and UIO sequences together in a checking sequence
TestCom'06 Proceedings of the 18th IFIP TC6/WG6.1 international conference on Testing of Communicating Systems
Reducing the lengths of checking sequences by overlapping
TestCom'06 Proceedings of the 18th IFIP TC6/WG6.1 international conference on Testing of Communicating Systems
Generalizing redundancy elimination in checking sequences
ISCIS'05 Proceedings of the 20th international conference on Computer and Information Sciences
New state-recognition patterns for conformance testing of finite state machine implementations
Computer Standards & Interfaces
The complexity of asynchronous model based testing
Theoretical Computer Science
On reducing test length for FSMs with extra states
Software Testing, Verification & Reliability
Computers in Biology and Medicine
Hi-index | 14.98 |
A checking sequence, generated from a finite state machine, is a test sequence that is guaranteed to lead to a failure if the system under test is faulty and has no more states than the specification. The problem of generating a checking sequence for a finite state machine M is simplified if M has a distinguishing sequence: an input sequence \bar{D} with the property that the output sequence produced by M in response to \bar{D} is different for the different states of M. Previous work has shown that, where a distinguishing sequence is known, an efficient checking sequence can be produced from the elements of a set A of sequences that verify the distinguishing sequence used and the elements of a set \Upsilon of subsequences that test the individual transitions by following each transition t by the distinguishing sequence that verifies the final state of t. In this previous work, A is a predefined set and \Upsilon is defined in terms of A. The checking sequence is produced by connecting the elements of \Upsilon and A to form a single sequence, using a predefined acyclic set E_c of transitions. An optimization algorithm is used in order to produce the shortest such checking sequence that can be generated on the basis of the given A and E_c. However, this previous work did not state how the sets A and E_c should be chosen. This paper investigates the problem of finding appropriate A and E_c to be used in checking sequence generation. We show how a set A may be chosen so that it minimizes the sum of the lengths of the sequences to be combined. Further, we show that the optimization step, in the checking sequence generation algorithm, may be adapted so that it generates the optimal E_c. Experiments are used to evaluate the proposed method.