A protocol test generation procedure
Computer Networks and ISDN Systems
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Fast Sequential ATPG Based on Implicit State Enumeration
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Reduced Length Checking Sequences
IEEE Transactions on Computers
Testing from Partial Deterministic FSM Specifications
IEEE Transactions on Computers
Separating sequence overlap for automated test sequence generation
Automated Software Engineering
Optimizing the Length of Checking Sequences
IEEE Transactions on Computers
Conditions for avoiding controllability problems in distributed testing
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Eliminating redundant tests in a checking sequence
TestCom'05 Proceedings of the 17th IFIP TC6/WG 6.1 international conference on Testing of Communicating Systems
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A test generation procedure to detect multiple state-table faults in finite-state machines is proposed. The importance of multiple state-table faults and their advantages as test generation objectives to avoid the need for checking experiments are considered. The proposed procedure is based on a new method for implicit enumeration of large numbers of multiple faults by using incompletely specified faulty machines. Experimental results are presented to demonstrate the effectiveness of implicit fault enumeration in detecting large numbers of multiple faults and in guaranteeing detection of all the faults or all the faults up to a specific multiplicity.