Digital design principles and practices
Digital design principles and practices
On Minimizing the Lengths of Checking Sequences
IEEE Transactions on Computers
Functional Tests for Scan Chain Latches
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IEEE Transactions on Computers
Fault detection experiments for asynchronous sequential machines
SWAT '70 Proceedings of the 11th Annual Symposium on Switching and Automata Theory (swat 1970)
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Test sequence generation for controller verification and test with high coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On state reduction of incompletely specified finite state machines
Computers and Electrical Engineering
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An algorithm for generating checking sequences forasynchronous finite state machines is proposed. Achecking sequence distinguishes a finite state machine(FSM) from all other FSMs with the same inputs andoutputs, and with the same or fewer number of states.This algorithm is applied to normal fundamental modeasynchronous finite state machines (AFSM). The derived checking sequences can be used either as a testsets that detect all logic faults or to verify that the circuit design is a correct implementation of the AFSM.The resulting test is guaranteed to detect all logic faultsoccurring in the machine even if the defect causes alimited number of additional states.