Learning regular sets from queries and counterexamples
Information and Computation
A fast state reduction algorithm for incompletely specified finite state machine
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis of Finite State Machines: Functional Optimization
Synthesis of Finite State Machines: Functional Optimization
CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines
Proceedings of the conference on Design, automation and test in Europe
An n log n algorithm for minimizing states in a finite automaton
An n log n algorithm for minimizing states in a finite automaton
Checking Sequence Generation for Asynchronous Sequential Elements
ITC '99 Proceedings of the 1999 IEEE International Test Conference
State Reduction in Incompletely Specified Finite-State Machines
IEEE Transactions on Computers
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
On the Synthesis of Finite-State Machines from Samples of Their Behavior
IEEE Transactions on Computers
Exact and heuristic algorithms for the minimization of incompletely specified state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TestCom '08 / FATES '08 Proceedings of the 20th IFIP TC 6/WG 6.1 international conference on Testing of Software and Communicating Systems: 8th International Workshop
Detecting Communication Protocol Security Flaws by Formal Fuzz Testing and Machine Learning
FORTE '08 Proceedings of the 28th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Canonical finite state machines for distributed systems
Theoretical Computer Science
Iterative refinement of specification for component based embedded systems
Proceedings of the 2011 International Symposium on Software Testing and Analysis
Minimization of incompletely specified mealy finite-state machines by merging two internal states
Journal of Computer and Systems Sciences International
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State reduction of incompletely specified finite state machines (ISFSMs) is an important task in optimization of sequential circuit design and known as an NP-complete problem. Removal of redundant states reduces the logic, because of this, chip area decreases. In addition, test generation is easier when the sequential circuit is irredundant. In this paper, we present a heuristic for state reduction of ISFSMs. The proposed heuristic is based on a branch-and-bound search technique and identification of sets of compatible states of a given ISFSM specification. We have obtained results as good as the best exact method in the literature but with significantly better run-times.