Testing from Partial Deterministic FSM Specifications
IEEE Transactions on Computers
On state reduction of incompletely specified finite state machines
Computers and Electrical Engineering
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A heuristic is proposed for state reduction in incompletelyspecified finite state machines (ISFSMs). The algorithm isbased on checking sequence generation and identificationof sets of compatible states. We have obtained results asgood as the best exact method in the literature but withsignificantly better run-times. In addition to finding areduced FSM, our algorithm also generates an I/Osequence that can be used as test vectors to verify theFSM麓s implementation.