Introduction to VLSI Systems
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Design of Diagnosable Sequential Machines Utilizing Extra Outputs
IEEE Transactions on Computers
An Improved Algorithm for Deriving Checking Experiments
IEEE Transactions on Computers
Sequential Network Design Using Extra Inputs for Fault Detection
IEEE Transactions on Computers
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Easily Testable Sequential Machines with Extra Inputs
IEEE Transactions on Computers
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
An Improved Bound on the Length of Checking Experiments for Sequential Machines with Counter Cycles
IEEE Transactions on Computers
Testable Design of Single-Output Sequential Machines Using Checking Experiments
IEEE Transactions on Computers
An Alternative to Scan Design Methods for Sequential Machines
IEEE Transactions on Computers - The MIT Press scientific computation series
| Hi-index | 14.98 |
A new approach to the testing of sequential machines is presented which employs signature analysis. In the conventional scheme of testing sequential finite state machines, distinguishing and transfer sequences are used. For the purposes of testing sequential machines by signature analysis, a signature distinguishing sequence is defined. An algorithm for augmenting a sequential machine by introducing an extra input is presented. This yields a sequential machine that has a signature distinguishing sequence. The additional cost in terms of the chip area for a programmable logic array (PLA) implementation is calculated.