Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Signature Analysis for Multiple-Output Circuits
IEEE Transactions on Computers
A unified view of test compression methods
IEEE Transactions on Computers
A method for generating weighted random test pattern
IBM Journal of Research and Development
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
A concept for test and reconfiguration of a fault-tolerant VLSI processor system
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Fault-Tolerant Computing: An Introduction and a Perspective
IEEE Transactions on Computers
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Measures of the Effectiveness of Fault Signature Analysis
IEEE Transactions on Computers
A Module-Level Testing Approach for Combinational Networks
IEEE Transactions on Computers
On Monte Carlo Testing of Logic Tree Networks
IEEE Transactions on Computers
Testing by Feedback Shift Register
IEEE Transactions on Computers
Pseudorandom Arrays for Built-In Tests
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
High-level safety mechanisms for safety-critical application-specific low power devices
ICCOMP'05 Proceedings of the 9th WSEAS International Conference on Computers
A combinatorial approach to X-tolerant compaction circuits
IEEE Transactions on Information Theory
Optimal scheduling of signature analysis for VLSI testing
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Signature Testing of Sequential Machines
IEEE Transactions on Computers
Parallel pseudorandom sequences for built-in test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A built-in test methodology for VLSI data paths
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
| Hi-index | 15.08 |
Advances in integrated circuit technology are decreasing acquisition cost per function of digital hardware while system software costs are increasing. The hardware advances allow practical implementation of more sophisticated and complex systems which have fewer components, but which may present severe test and maintenance problems due to their complexity. As a result, the use of built-in test (BIT) hardware in place of software becomes increasingly attractive. The Navy funded Advanced Avionics Fault Isolation System (AAFIS) concept utilizes BIT logic for cost-effective fault detection and fault isolation to a digital subsystem and to the faulty module therein. Added logic, available at low cost with advanced microelectronics, is used to perform test pattern generation in each subsystem and to code over the test sequence the outputs and test points on each subsystem module. The coded test response is compared to a predetermined constant. The OR of resulting module pass-fail signals indicates subsystem faults, while identification of a module fail signal provides isolation to a faulty module. Practical coding techniques are presented, with tradeoff of speed, test effectiveness and logic requirements for each. BIT logic design and simulation results verify high fault detection and moderate added logic for BIT.