Efficient Generation of Statistically Good Pseudonoise by Linearly Interconnected Shift Registers
IEEE Transactions on Computers
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
10.2 Design of Phase Shifters for BIST Applications
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A compact 1.1-Gb/s encoder and a memory-based 600-Mb/s decoder for LDPC convolutional codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
| Hi-index | 14.98 |
Parallel pseudorandom sequences for use in built-in test are discussed. The two-dimensional nature of these sequences-makes it natural to consider the resulting binary arrays. Some of the desired properties of such arrays are discussed, as well as some of the problems. Generators for such arrays are described. A conventional LFSR with parallel output is shown to be a poor choice for such a generator. Several compact generators are described, which are shown to be compromises between complexity and varying degrees of implementation of the desired properties in the resulting sequences. One of the compact generators produces sequences which have the desired properties for built-in tests.