Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
IEEE Spectrum
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Using BIST Control for Pattern Generation
Proceedings of the IEEE International Test Conference
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Deterministic BIST with Partial Scan
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Point Placement to Simplify Fault Detection
IEEE Transactions on Computers
Pseudorandom Arrays for Built-In Tests
IEEE Transactions on Computers
Circuit partitioning for efficient logic BIST synthesis
Proceedings of the conference on Design, automation and test in Europe
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Journal of Electronic Testing: Theory and Applications
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures
Journal of Electronic Testing: Theory and Applications
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits
Journal of Electronic Testing: Theory and Applications
A highly regular multi-phase reseeding technique for scan-based BIST
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Tackling Test Trade-offs from Design, Manufacturing to Market using Economic Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Case Study on t e Implementation of t e Illinois Scan Architecture
ITC '01 Proceedings of the 2001 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
X-masking during logic BIST and its impact on defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
IEICE - Transactions on Information and Systems
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present the application of a deterministic logicBIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage canbe achieved for industrial circuits up to 100K gates with10,000 test patterns, at a total area cost for BIST hardwareof typically 5%-15%. It is demonstrated that a tradeoffis possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertionno modifications of the circuit under test are required,complete fault efficiency is guaranteed, and theimpact on the design process is minimized.