Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Scan-Path Architecture for Pseudorandom Testing
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Two-Dimensional Test Data Decompressor for Multiple Scan Designs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Using BIST Control for Pattern Generation
Proceedings of the IEEE International Test Conference
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
10.2 Design of Phase Shifters for BIST Applications
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Pseudorandom Arrays for Built-In Tests
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Deterministic BIST with Partial Scan
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Circuit partitioning for efficient logic BIST synthesis
Proceedings of the conference on Design, automation and test in Europe
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
A scan BIST generation method using a markov source and partial bit-fixing
Proceedings of the 40th annual Design Automation Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A New FPGA for DSP Applications Integrating BIST Capabilities
Journal of Electronic Testing: Theory and Applications
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A deterministic BIST scheme for circuits withmultiple scan paths is presented. A procedure isdescribed for synthesizing a pattern generator whichstimulates all scan chains simultaneously andguarantees complete fault coverage.The new scheme may require less chip area than aclassical LFSR-based approach while better or evencomplete fault coverage is obtained at the same time.