Shift Register Sequences
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
A Hardware Approach to Self-Testing of Large Programmable Logic Arrays
IEEE Transactions on Computers
Linear Dependencies in Linear Feedback Shift Registers
IEEE Transactions on Computers
IEEE Transactions on Computers
Test Length for Pseudorandom Testing
IEEE Transactions on Computers
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
10.3 Distributed Generation of Weighted Random Patterns
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Test Point Insertion Algorithm for Mixed-Signal Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Modifying User-Defined Logic for Test Access to Embedded Cores
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
IEEE Transactions on Computers
Logic Test Pattern Generation Using Linear Codes
IEEE Transactions on Computers
Design and verification of the IBM system z10 I/O subsystem chips
IBM Journal of Research and Development
ASIC test cost/strategy trade-offs
ITC'94 Proceedings of the 1994 international conference on Test
Automated logic synthesis of random pattern testable circuits
ITC'94 Proceedings of the 1994 international conference on Test
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Enhancing random-pattern coverage of programmable logic arrays via masking technique
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Random testing for stuck-at storage cells in an embedded memory
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Sufficient testing in a self-testing environment
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power problems in VLSI circuit testing
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Embedded linear feedback shift registers can be used for logic component self-test. The issue of test coverage is addressed by circuit modification, where necessary, of random-pattern-resistant fault nodes. Also given is a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis.