Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Ternary Scan Design for VLSI Testability
IEEE Transactions on Computers
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
An intelligent compiler subsystem for a silicon compiler
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Test generation cost analysis and projections
25 years of DAC Papers on Twenty-five years of electronic design automation
SCOAP: Sandia controllability/observability analysis program
25 years of DAC Papers on Twenty-five years of electronic design automation
PODEM-X: An automatic test generation system for VLSI logic structures
25 years of DAC Papers on Twenty-five years of electronic design automation
Critical path tracing - an alternative to fault simulation
25 years of DAC Papers on Twenty-five years of electronic design automation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A method for generating weighted random test pattern
IBM Journal of Research and Development
Built-In Testing of Integrated Circuit Wafers
IEEE Transactions on Computers
The development of ultra-high-frequency VLSI device test systems
IBM Journal of Research and Development
Test generation for VLSI chips with embedded memories
IBM Journal of Research and Development
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
An ac test structure for fast memory arrays
IBM Journal of Research and Development
Gross delay defect evaluation for a CMOS logic design system product
IBM Journal of Research and Development
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
Design for testability and diagnosis in a VLSI CMOS System/370 processor
IBM Journal of Research and Development
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
RIDDLE: A Foundation for Test Generation on a High-Level Design Description
IEEE Transactions on Computers
IBM Enterprise System/900 Type 9121 system controller and memory subsystem design
IBM Journal of Research and Development
Design and performance of the IBM Enterprise System/900 Type 9121 Vector Facility
IBM Journal of Research and Development
IBM Journal of Research and Development
Sequential test generation at the register-transfer and logic levels
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Load Balancing in a Hybrid ATPG Environment
IEEE Transactions on Computers
Correlation-reduced scan-path design to improve delay fault coverage
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ATPG based on a novel grid-addressable latch element
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Delay test effectiveness evaluation of LSSD-based VLSI logic circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The IBM Enterprise Systems Connection (ESCON) channel: a versatile building block
IBM Journal of Research and Development
DAC '94 Proceedings of the 31st annual Design Automation Conference
A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing
IEEE Transactions on Parallel and Distributed Systems
Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Path delay ATPG for standard scan design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
On Dictionary-Based Fault Location in Digital Logic Circuits
IEEE Transactions on Computers
Standard-cell-based design methodology for high-performance support chips
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
CATAPULT: concurrent automatic testing allowing parallelization and using limited topology
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The performance of the concurrent fault simulation algorithms in MOZART
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Overall consideration of scan design and test generation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Functional fault modeling and simulation for VLSI devices
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
RTG: automatic register level test generator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A design rule database system to support technology-adaptable applications
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
High level hierarchical fault simulation techniques
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
Testing and Debugging Custom Integrated Circuits
ACM Computing Surveys (CSUR)
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Fault detection of MOS combinatorial networks
ACM SIGDA Newsletter
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Algorithms for Automatic Test-Pattern Generation
IEEE Design & Test
IEEE Design & Test
The Impact of Boundary Scan on Board Test
IEEE Design & Test
Scan-Path Architecture for Pseudorandom Testing
IEEE Design & Test
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Low-Cost Testing of High-Density Logic Components
IEEE Design & Test
IEEE Design & Test
Progress in Design for Test: A Personal View
IEEE Design & Test
IEEE Design & Test
Automated Diagnosis in Testing and Failure Analysis
IEEE Design & Test
Testability Features of the AMD-K6 Microprocessor
IEEE Design & Test
Testing the 500-MHz IBM S/390 Microprocessor
IEEE Design & Test
Random Pattern Testability of Delay Faults
IEEE Transactions on Computers
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer
IEEE Transactions on Computers
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Unified scan design with scannable memory arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
An RTL Methodology to Enable Low Overhead Combinational Testing
EDTC '97 Proceedings of the 1997 European conference on Design and Test
IBM FSD VLSI chip design methodology
DAC '83 Proceedings of the 20th Design Automation Conference
Test generation for scan design circuits with tri-state modules and bidirectional terminals
DAC '83 Proceedings of the 20th Design Automation Conference
Diagnosis of TCM failures in the IBM 3081 Processor complex
DAC '83 Proceedings of the 20th Design Automation Conference
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
A logic design front-end for improved engineering productivity
DAC '83 Proceedings of the 20th Design Automation Conference
Design For Test Calculus: An algorithm for DFT rules checking
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
An algebra for logic strength simulation
DAC '83 Proceedings of the 20th Design Automation Conference
Computer aided design (CAD) using logic programming
DAC '84 Proceedings of the 21st Design Automation Conference
Chip partitioning aid: A design technique for partitionability and testability in VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic test generation for stuck-open faults in CMOS VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
Placement of variable size circuits on LSI masterslices
DAC '81 Proceedings of the 18th Design Automation Conference
Contrasts in physical design between LSI and VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
Test data verification - not just the final step for test data before release for production testing
DAC '81 Proceedings of the 18th Design Automation Conference
A test methodology for large logic networks
DAC '78 Proceedings of the 15th Design Automation Conference
Selective controllability: A proposal for testing and diagnosis
DAC '78 Proceedings of the 15th Design Automation Conference
The evolution of design automation to meet the challanges of VLSI
DAC '80 Proceedings of the 17th Design Automation Conference
A new test pattern generation system
DAC '80 Proceedings of the 17th Design Automation Conference
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
Developments in verification of design correctness (A Tutorial)
DAC '80 Proceedings of the 17th Design Automation Conference
Digital test generation and design for testability
DAC '80 Proceedings of the 17th Design Automation Conference
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Verifying deep logic hierarchies with ALEX
DAC '80 Proceedings of the 17th Design Automation Conference
Complexity theory and design automation
DAC '80 Proceedings of the 17th Design Automation Conference
Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
IBM 3081 system overview and technology
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
An enhancement of lssd to reduce test pattern generation effort and increase fault coverage
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
A formal method for computer design verification
DAC '82 Proceedings of the 19th Design Automation Conference
Testing of MOS combinational networks a procedure for efficient fault simulation and test generation
DAC '79 Proceedings of the 16th Design Automation Conference
Behavioral-level test development
DAC '79 Proceedings of the 16th Design Automation Conference
Testability-oriented channel routing
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
ATPG for scan chain latches and flip-flops
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A practical approach to instruction-based test generation for functional modules of VLSI processors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
13.1 A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
1.1 Designing a Testable System on a Chip
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Token Scan Architecture for Low Power Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan Test Sequencing Hardware for Structural Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testability Features of AMD-K6" Microprocessor
ITC '97 Proceedings of the 1997 IEEE International Test Conference
SCAN SYNTHESIS FOR ONE-HOT SIGNALS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testing the Enterprise IBM System/390" Multi Processor
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testing The 400-MHz IBM Generation-4 CMOS Chip
ITC '97 Proceedings of the 1997 IEEE International Test Conference
SO WHAT IS AN OPTIMAL TEST MIX? A DISCUSSION OF THE SEMATECH METHODS EXPERIMENT
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods Data
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design for Testability: It is time to deliver it for Time-to-Market
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Embedded X86 Testing Methodology
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Test and Debug Features of the AMD-K7TM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Tools and devices supporting the pseudo-exhaustive test
EURO-DAC '90 Proceedings of the conference on European design automation
Accelerated test pattern generation by cone-oriented circuit partitioning
EURO-DAC '90 Proceedings of the conference on European design automation
MACHETE: synthesis of sequential machines for easy testability
EURO-DAC '91 Proceedings of the conference on European design automation
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IBM Journal of Research and Development
A CMOS LSSD test generation system
IBM Journal of Research and Development
A multi-purpose VLSI chip for adaptive data compression of bilevel images
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
SoC Design and Test Considerations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
Fault Diagnosis of MOS Combinational Networks
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
The Bidirectional Double Latch (BDDL)
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Built-In Testing of One-Dimensional Unilateral Iterative Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Diagnosis of Systems with Asymmetric Invalidation
IEEE Transactions on Computers
Redundancy and Don't Cares in Logic Synthesis
IEEE Transactions on Computers
A Class of Test Generators for Built-In Testing
IEEE Transactions on Computers
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
An Inductive Assertion Method for Register Transfer Level Design Verification
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
New directions for micro- and system architectures in the 1980s
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Detectability of internal bridging faults in scan chains
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A new delay test based on delay defect detection within slack intervals (DDSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Design automation and the programmable logic array macro
IBM Journal of Research and Development
S/390 G5 CMOS microprocessor diagnostics
IBM Journal of Research and Development
Reliability, availability, and serviceability of IBM computer systems: a quarter century of progress
IBM Journal of Research and Development
Semiconductor logic technology in IBM
IBM Journal of Research and Development
IBM Journal of Research and Development
System development and technology aspects of the IBM 3081 processor complex
IBM Journal of Research and Development
IBM 3081 processor unit: design considerations and design process
IBM Journal of Research and Development
Automated diagnostic methodology for the IBM 3081 processor complex
IBM Journal of Research and Development
Design verification system for large-scale LSI designs
IBM Journal of Research and Development
Physical design of a custom 16-bit microprocessor
IBM Journal of Research and Development
Design considerations for a VLSI microprocessor
IBM Journal of Research and Development
Bipolar chip design for a VLSI microprocessor
IBM Journal of Research and Development
A VLSI design verification strategy
IBM Journal of Research and Development
A bipolar VLSI custom macro physical design verification strategy
IBM Journal of Research and Development
Product quality level monitoring and control for logic chips and modules
IBM Journal of Research and Development
Multi-chip module test and diagnostic methodology
IBM Journal of Research and Development
The LT1280 for through-the-pins testing of the thermal conduction module
IBM Journal of Research and Development
Failure diagnosis on the LT1280
IBM Journal of Research and Development
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Blue Gene/L compute chip: control, test, and bring-up infrastructure
IBM Journal of Research and Development
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Balancing structured and ad-hoc design for test: testing of the PowerPC 603TMmicroprocessor
ITC'94 Proceedings of the 1994 international conference on Test
ASIC test cost/strategy trade-offs
ITC'94 Proceedings of the 1994 international conference on Test
Hybrid design for testability combining scan and clock line control and method for test generation
ITC'94 Proceedings of the 1994 international conference on Test
On synthesizing circuits with implicit test ability constraints
ITC'94 Proceedings of the 1994 international conference on Test
A simulation-based protocol-driven scan test design rule checker
ITC'94 Proceedings of the 1994 international conference on Test
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Testability features in the TMS370 family of microcomputers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Expert system for the functional test program generation of digital electronic circuit boards
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Fault detection effectiveness of weighted random patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Identification of failing tests with cycling registers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A test and maintenance controller for a module containing testable chips
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Reconfigurable hardware for Pseudo-exhaustive test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Synthesis and optimization procedures for fully and easily testable sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An expert test program generation system for per-pin testers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An incomplete scan design approach to test generation for sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 1: concepts and coverage metrics
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 2: algebra and algorithms
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Using scan technology for debug and diagnostics in a workstation environment
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Scan diagnostic strategy for the series 10000 PRISM workstation
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Partial hardware partitioning: a new pseudo-exhaustive test implementation
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing
IEEE Transactions on Computers
Signature Testing of Sequential Machines
IEEE Transactions on Computers
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic test pattern generation for asynchronous networks
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Higher certainty of error coverage by output data modification
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Sufficient testing in a self-testing environment
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
CMOS fault testing: multiple faults in combinational circuits single fault in sequential circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Pseudo-exhaustive testing of sequential machines using signature analysis
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A built-in test methodology for VLSI data paths
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Testability analysis of MOS VLSI circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A vote in favor of fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A technique for making asynchronous sequential circuits readily testable
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
On CMOS totally self-checking circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LSI logic testing: an overview
IEEE Transactions on Computers
Global convergence analysis of mixed-signal systems
Proceedings of the 48th Design Automation Conference
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.11 |
The ability to put hundreds of logic gates on a single chip of silicon offers great potential for reducing power, increasing speed, and reducing cost. Unfortunately, several problems must be solved in order to exploit these advantages of large-scale integration, LSI. This paper will describe a logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI. The design method is based on two concepts that are nearly independent but combine efficiently and effectively. The first is to design sequential logic structures so that correct operation is not dependent on signal rise and fall time or on circuit or wire delay. The second is to design all the internal storage elements (other than memory arrays) so that they can also be operated as shift registers to facilitate testing and diagnostics. Sequential logic, which is difficult to test, can then be transformed to combinational logic, which is less difficult. The transformation is performed during test generation. Advantages and cost impact will also be discussed qualitatively.