Fault-tolerant computing: theory and techniques; vol. 1
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
A new integrated system for PLA testing and verification
DAC '83 Proceedings of the 20th Design Automation Conference
Testing for bridging faults (shorts) in CMOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Higher certainty of error coverage by output data modification
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present-day automatic test pattern generation (ATPG) programs. Fault simulation is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher - all irredundant multiple as well as single stuck faults are detected. Test length is easily controlled. The test patterns are easily generated algorithmically either by program or hardware.