Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Design for Testability A Survey
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Built in self testing for detection of coupling faults in semiconductor memories
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Logic Test Pattern Generation Using Linear Codes
IEEE Transactions on Computers
A coding algorithm for constant weight vectors: a geometric approach based on dissections
IEEE Transactions on Information Theory
Constraint-Based approaches to the covering test problem
CSCLP'04 Proceedings of the 2004 joint ERCIM/CoLOGNET international conference on Recent Advances in Constraints
Journal of Electronic Testing: Theory and Applications
Antirandom Test Vectors for BIST in Hardware/Software Systems
Fundamenta Informaticae
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We develop in this paper a simple way of generating a test set which simultaneously provides exhaustive pattern testing with respect to all input subsets of a logic circuit up to a certain size. It is shown that such a test set may be formed with vectors of a particular set of weights. Main theorems and examples are established and illustrated in the binary case (for 2-value logic circuits) and then generalized to nonbinary cases (for multivalue logic circuits). Such test sets are simple in structure and become optimal in size in certain cases. It is also shown that such a test set can be effectively implemented via a scan path type shifter.