A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
An integrated debugging system based on E-beam test
Microelectronic Engineering
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design Of A Universal BIST (UBIST) Structure
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
BIST-Based Diagnostics of FPGA Logic Blocks
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Incorporating Physical Design-For-Test Into Routing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Do you practice safe test? what we found out about your habits
ITC'94 Proceedings of the 1994 international conference on Test
Reconfigurable hardware for Pseudo-exhaustive test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the testing of multiplexers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An analysis of the multiple fault detection capabilities of single stuck-at fault test sets
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Pseudo-exhaustive testing of sequential machines using signature analysis
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bounds on pseudoexhaustive test lengths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AsiaSim'04 Proceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications
| Hi-index | 14.99 |
A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher all irredundant multiple as well as single stuck faults are detected. The test patterns are easily generated algorithmically either by program or hardware.