Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS)
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Synthesis of one-dimensional linear hybrid cellular automata
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cellular automata-based pseudorandom number generators for built-in self-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time
Journal of Electronic Testing: Theory and Applications
CA based cost optimized PRNG for Monte-Carlo simulation of distributed computation
Proceedings of the CUBE International Information Technology Conference
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This paper introduces a Built-In Self Test(BIST) structure referred to as Universal BIST (UBIST).The Test Pattern Generator (TPG) of the proposed UBISTis designed to generate an one of the three classes of testpatterns - deterministic, pseudo-exhaustive, and pseudo-random- to satisf the specific test requirement of a CircuitUnder Test (CUT). Further, while generating the pseudo-randomtest patterns, the TPG can avoid generation of agiven set of patterns declared prohibited for the CUT. Thetheoretical framework of CA noted in [1] has provided thefoundation of this work. Effectiveness of the UBIST structureis validated through extensive experimentation.