Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS)

Authors:
Niloy Ganguly;Biplab K. Sikdar;P P. al Chaudhuri
Affiliations:
Computer centre, IISWBM, Calcutta, West Bengal, India;Department of Computer Sc & Technology , Bengal Engineering College (D U), Howrah, India;Department of Computer Sc & Technology , Bengal Engineering College (D U), Howrah, India
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

This paper reports the design of a T est P attern Generator (TPG) for V LSI circuits. The on-chip TPG is so designed that it generates test patterns while avoiding generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-random quality of the test patterns generated.The experimental results confirm high quality of randomness while ensuring fault coverage close to the figures achieved with a typical Pseudo Random Pattern Generator (PRPG) designed around maximal length LFSR=CA. Compared to the conventional PRPG it incurs no additional cost.