Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Analysis and simulation of parallel signature analyzers
Computers and Mathematics with Applications - Diagnosis and reliable design of VLSI systems
Syndrome and transition count are uncorrelated
IEEE Transactions on Information Theory
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
A Statistical Theory of Digital Circuit Testability
IEEE Transactions on Computers
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Optimizing error masking in BIST by output data modification
Journal of Electronic Testing: Theory and Applications
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
Structured Logic Testing
Shift Register Sequences
Economic Effects in Design and Test
IEEE Design & Test
An efficient procedure for the synthesis of fast self-testable controller structures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Random Pattern Testability of Memory Control Logic
IEEE Transactions on Computers
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
An IEEE 1149.1 Compliant Test Control Architecture
Journal of Electronic Testing: Theory and Applications
Efficient BIST hardware insertion with low test application time for synthesized data paths
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Built-in Self Test Based on Multiple On-Chip Signature Checking
Journal of Electronic Testing: Theory and Applications
A novel reseeding technique for accumulator-based test pattern generation
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
A synthesis procedure for flexible logic functions
Proceedings of the conference on Design, automation and test in Europe
Random limited-scan to improve random pattern testing of scan circuits
Proceedings of the 38th annual Design Automation Conference
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Design for Testability in Hardware-Software Systems
IEEE Design & Test
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A New Survival Architecture for Network Processors
AISA '02 Proceedings of the First International Workshop on Advanced Internet Services and Applications
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Theory and applications of cellular automata for synthesis of easily testable combinational logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Multiplicative Window Generators of Pseudo-random Test Vectors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Novel BIST Architecture With Built-in Self Check
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design Of A Universal BIST (UBIST) Structure
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Mutual Testing based on Wavelet Transforms
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DESIGN OF COMPACTORS FOR SIGNATURE-ANALYZERS IN BUILT-IN SELF-TEST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Highly-Efficient Transparent Online Memory Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
FAULT DIAGNOSIS IN-SCAN-BASED BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ON-CHIP MEASUREMENT OF THE JITTER TRANSFER FUNCTION OF CHARGE-PUMP PHASE-LOCKED LOOPS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Parameterizable Testing Scheme for FIR Filters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Emulating static faults using a Xilinx based emulator
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Efficient BIST design for sequential machines using FiF-FoF values in machine states
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Simultaneous reduction in test data volume and test time for TRC-reseeding
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
An approach to test determination for programmable logic arrays
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
A test set embedding approach based on twisted-ring counter with few seeds
Integration, the VLSI Journal
Fault tolerant techniques for reconfigurable platforms
Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India
Keynote speech: testing methodologies for embedded systems and systems-on-chip
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Increasing embedding probabilities of RPRPs in RIN based BIST
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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An overview of built-in self-test (BIST) principles and practices is presented. The issues and economics underlying BIST are discussed, and the related hierarchical test structures are introduced. The fundamental BIST concepts of pattern generation and response analysis are explained. Linear feedback shift register theory is reviewed.