A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Successful ASIC Design the First Time Through
Successful ASIC Design the First Time Through
Analysis of Testable PLA Designs
IEEE Design & Test
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
Tackling cost optimization in testable design by forward inferencing
EURO-DAC '92 Proceedings of the conference on European design automation
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Analyzing Multichip Module Testing Strategies
IEEE Design & Test
ITC '97 Proceedings of the 1997 IEEE International Test Conference
System test cost modelling based on event rate analysis
ITC'94 Proceedings of the 1994 international conference on Test
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The authors argue that because of misconceptions and myths about the cost of test, many devices and systems are inadequately tested. Focusing on application-specific integrated circuits (ASICs), the authors discuss the economics of test and show how economic analysis leads to test that pays back. The EVEREST test strategy planner, a design tool that aids in the selection of design-for-testability structures during ASIC design and uses cost as a primary selection parameter, is presented.