PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A knowledge based TDM selection system
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Test generation for programmable logic arrays
DAC '82 Proceedings of the 19th Design Automation Conference
A Knowledge-Based System for Selecting Test Methodologies
IEEE Design & Test
Economic Effects in Design and Test
IEEE Design & Test
Exploring Test Space with Fuzzy Decision Making
IEEE Design & Test
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A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, and fully testable PLAs. The attributes that make a good testable design are then discussed. They fall into four categories: (1) testability characteristics; (2) effect on original design; (3) requirements of the application environment; and (4) design costs, i.e. how difficult it is to implement the technique.