Logic Design and Switching Theory
Logic Design and Switching Theory
DAC '78 Proceedings of the 15th Design Automation Conference
Lower Overhead Design for Testability of Programmable Logic Arrays
IEEE Transactions on Computers - The MIT Press scientific computation series
IEEE Transactions on Computers
The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits
IEEE Transactions on Computers
PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Optimal order of the VLSI IC testing sequence
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A New Method for Testing Re-Programmable PLAs
Journal of Electronic Testing: Theory and Applications
Analysis of Testable PLA Designs
IEEE Design & Test
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs
Proceedings of the conference on Design, automation and test in Europe
Testability features of the MC68020
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Lower overhead design for testability of programmable logic arrays
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Defect-tolerant logic hardening for crossbar-based nanosystems
Proceedings of the Conference on Design, Automation and Test in Europe
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The problem of fault detection and test generation for programmable logic arrays (PLAs) is investigated. The effect of actual physical failures is viewed in terms of the logical changes of the product terms (growth, shrinkage, appearance and disappearance) constituting the PLA. Methods to generate a minimal single fault detection test set (Ts) from the product term specification of the PLAs, are presented. It is shown that such a test set can be derived using a set of simple, easily implementable algorithms. Methods to augment Ts in order to obtain a multiple fault detection test set (TM) are also presented.